Recently, SiC is attracting attention as the semiconductor material for the next generation. SiC has a dielectric breakdown field of 6 MV/cm that is approximately one order of magnitude greater than that of silicon (Si). This high dielectric breakdown property of SiC may provide favorable characteristics for a semiconductor device that could not be realized with Si type semiconductor devices that are the present mainstream. Particularly the high breakdown voltage and low loss of SiC semiconductor devices lead to the strong demand for practical use of realizing power conversion devices such as small and highly-efficient inverters and converters in the field of electric power, trains, vehicles, electrical appliance and the like.
As such a SiC semiconductor device, there is proposed an insulating gate type semiconductor device, particularly a vertical MOSFET (MOS Field Effect Transistor; metal-oxide film-semiconductor field effect transistor) of the DMOS (Double Diffused Metal Oxide Semiconductor) structure (refer to U.S. Pat. No. 3,498,459 (Patent Literature 1)). According to Patent Literature 1, the vertical MOSFET includes a p base (body) region, an n+ source region, and an n+ drain region made of silicon carbide; a gate insulating film formed at the surface of the p base region, a gate electrode provided on the gate insulating film, and two main electrodes for current flow. The current between the main electrodes is controlled by applying positive voltage to the gate electrode and adjusting the concentration of electrons in the inversion layer induced at the surface layer of the p base region located below the gate insulating film.